1. Field of the Invention
This invention relates to clock phase alignment, and more particularly to clock phase alignment for clocks derived from a common source but which, due to differing clock frequencies, are seldom, if ever, aligned with one another.
2. Related Art
Computer systems have numerous subsystems and components, some of which operate at different clock speeds. For example, a central processing unit (“CPU”) may operate at 500 MHz, while a memory unit operates at 100 MHz. This is true for a system with numerous discrete components as well as a system-on-chip (“SOC”) that is highly integrated and has a number of different subsystems on a single chip.
It is common in SOC clocking systems and other systems to use a single phase locked loop (“PLL”) as a source to create numerous primary clocks with different frequencies. It is also common to derive other clocks from the primary clocks by additional clock generation logic circuitry. To achieve efficient communication in such systems it is often necessary to phase align all these clocks. However, while PLL's generally ensure phase alignment among such primary clocks, they cannot guarantee phase alignment in the other clocks derived from the primary clocks.
Since these clocks do not all have the same frequency, it is difficult to periodically align them. That is, many conventional circuits for aligning clocks depend on the clocks sharing a fundamental frequency. Also, many conventional phase alignment circuits are too slow to align high speed clocks. Thus, a need exists for methods and circuitry for aligning high-speed clocks, particularly if the clocks have different frequencies.